HLF 74LS112 Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear – DIP16 | High-Speed TTL Logic IC | 4.75V–5.25V, 0°C to +70°C | Through-Hole Package

The HLF 74LS112 is a Dual J-K negative-edge-triggered flip-flop IC designed using Low-Power Schottky TTL (LS) technology for high-speed, low-power digital logic applications. Each flip-flop provides J, K, Clock, Preset, and Clear inputs, enabling toggle, set, reset, and hold functions with negative-edge clock triggering for precise timing control.

This IC is ideal for frequency division, binary counters, sequential logic circuits, and state machine design, where synchronized transitions and reliable asynchronous preset/clear control are critical. The integrated Preset and Clear inputs allow outputs to be set or reset independently of the clock, providing flexible initialization and control.

Key Features:

• Function: Dual J-K Negative-Edge-Triggered Flip-Flops with Preset and Clear

• Technology: Low-Power Schottky TTL (LS Series)

• Operating Voltage: 4.75V – 5.25V

• Operating Temperature: 0°C to +70°C

• Package Type: DIP16 (Dual In-Line Package)

• Mounting Type: Through-Hole

• Negative-Edge Clock Triggering: Ensures accurate and stable transitions

• Asynchronous Preset and Clear Inputs: Flexible output initialization

• High-Speed TTL Logic Performance

• Low Power Dissipation: Efficient LS design

Applications:

• Frequency Division and Binary Counters

• Sequential Logic and Control Systems

• Digital Toggle and Timing Circuits

• State Machine and Register Design

• Educational and Prototype Electronics